Semiconductor wafers comprising a plurality of micro-machined components are well known. Additionally, semiconductor wafers which comprise a plurality of micro-machined micro-mirrors are also well known. For example, U.S. Pat. No. 6,201,631 of Greywall discloses such a semiconductor wafer and also a method for fabricating such a wafer. In general, the micro-mirrors of such semiconductor wafers are arranged in a matrix array formed by a plurality of spaced apart rows and spaced apart columns. Any number of micro-mirrors may be provided, for example, a sixteen by sixteen array of two hundred and fifty-six micro-mirrors is commonly provided. Indeed, it is known to provide micro-mirror arrays of array sizes of two by two arrays up to one thousand by one thousand arrays and even greater.
Typically, such semiconductor wafers comprising an array of micro-mirrors comprise a support substrate, typically a base substrate and a component substrate which are bonded together. The component substrate comprises a handle layer which supports a membrane layer in which the micro-mirrors are formed. Cavities are formed in the handle layer for exposing the micro-mirrors through the handle layer. Typically, a buried oxide layer is located between the membrane layer and the handle layer, and after etching of the cavities in the handle layer the oxide layer adjacent the micro-mirrors is etched for exposing the micro-mirrors through the cavities in the handle layer. Electrodes are formed on the base substrate at appropriate locations, so that when the component substrate is bonded to the base substrate the electrodes are appropriately aligned with the corresponding micro-mirrors through the cavities in the handle layer, for co-operating with the micro-mirrors for tilting thereof.
The handle layer acts as a spacer for spacing the membrane layer with the micro-mirrors formed therein apart from the base substrate, and in turn the electrodes formed thereon for facilitating tilting of the micro-mirrors. The depth by which the handle layer spaces the membrane layer from the base substrate is largely determined by the area of the mirrors, and the maximum angle of tilt required. However, in general, it is desirable that the spacing between the membrane layer and the base substrate should be relatively small so that the electrodes on the base substrate are relatively close to the micro-mirrors, thereby minimising the voltages required on the electrodes for tilting the mirrors. Typically, desired spacings between the base substrate and the membrane layer are in the range of 10 μm to 200 μm. This requires that the handle layer which is supporting the membrane layer must be machined to a depth of between 10 μm and 200 μm, depending on the desired spacing, prior to bonding to the base substrate. This results in a serious problem in that in general, it is desirable that the handle layer should be of a depth of at least 350 μm, and preferably 500 μm for supporting the membrane layer until the membrane layer is otherwise supported, for example, by the base substrate. Thus, by having to reduce the depth of the handle layer to between 10 μm to 200 μm there is a considerable risk of damage to the membrane layer and the micro-mirrors while the membrane layer is supported only by the thin handle layer, until the component layer is bonded to the base substrate. This is undesirable.
There is therefore a need for a semiconductor wafer comprising a plurality of micro-mirrors, or indeed, any other micro-machined components which overcomes this problem. There is also a need for a method for fabricating a semiconductor wafer having a plurality of micro-mirrors or other micro-machined components which similarly overcomes the problem.
The present invention is directed towards providing such a semiconductor wafer and a method.